EUVL Symposium
Oct 05, 2015 - Oct 07, 2015

Forum 100
Maastricht, GV 6229

Enabling EUVL HVM Introduction for the 7 nm logic technology node

The first generation of EUVL production tools is in the field and chip manufacturers and the supply chain are focused on driving EUVL Technology toward meeting HVM productivity and yield targets for the 7 nm technology logic node, unless memory companies accelerate their EUV introduction.

It was concluded in last year's symposium that there are remaining challenges where further progress is still required to achieve this objective, including:

  • Meeting productivity and availability targets for HVM
  • Mature mask handling/mask yield & defect inspection/review/repair infrastructure
  • Simultaneous achievement of resist resolution, sensitivity and LER, including the use of post-processing techniques
  • EUV patterning: defectivity, variability, stack and pattern transfer
  • Hybrid 193i/EUV/DSA insertion
Extending EUVL technology to sub- 7 nm logic technology nodes
To meet the challenges beyond the 7nm logic technology nodes, the industry needs to explore new innovative approaches in EUV source, mask, and imaging materials.  For any of the EUVL extension paths to be viable, much higher power sources will be needed.
  • Mask: novel absorber types, mask architectures reducing mask 3D effects, phase-shift
  • EUV pellicle technologies
  • Novel EUV resists and auxiliary materials
  • EUV extensions (high NA, including anamorphic, double patterning, lower wavelengths, ...)
  • Alternative black-border solutions
  • Out-of-band suppression solutions
  • > 0.5 kW EUV light sources