About the Panelists

Barbara De Salvo
Silicon Technology Strategist 
Augmented-Reality-Virtual-Reality Silicon Division 
Facebook, Inc. 

Before joining Facebook this year, Barbara De Salvo was Chief Scientist and Deputy Director of CEA-Leti. She founded and led the advanced memory technology division, introducing disruptive technologies (e.g., phase-change, resistive oxide-based, and conductive-bridge) for embedded and stand-alone applications. She also pioneered neuromorphic hardware solutions based on emerging memory technologies for ultra-low-power cognitive systems. Previously, she was manager and visiting scholar at IBM-Albany-NY under the sub-10nm CMOS Technology Alliance, contributing to silicon-on-insulator, finfet, and stacked nanowire development. She has authored more than 300 referred articles, 10 book chapters, and a monograph on Silicon Non-Volatile Memories edited by Wiley and Sons. She serves on the IEEE IEDM Executive Committee. She holds a Ph.D. in microelectronics from the Institut Polytechnique de Grenoble.
 

Bala Haran, Ph.D.
IBM Master Inventor and 
Director of Si Process Research
IBM Research Corporation

Bala Haran heads IBM's Semiconductor Process Technology Research and AI Hardware Prototyping, driving process strategy and research on scaling and AI prototyping. Previously, he led multi-integration teams driving replacement metal gate finfets at the 14nm, 10nm, and 7nm generations. These efforts culminated in technology feasibility demonstrations vital for the introduction of IBM's 14nm SOI finfet product and its partners’ mobile platforms at 10nm. Earlier, he was a member of the team that introduced the industry's first NiPt salicide process at the 65nm node and successfully transferred it worldwide. He earned a Ph.D. in chemical engineering from the University of South Carolina.
 

Ramune Nagisetty
Senior Principal Engineer and 
Director of Process and Product Integration
Technology Development Group
Intel Corporation

In her current position, Ramune Nagisetty has championed the use of chiplets and package-level integration to reduce portfolio cost, scale innovation, and speed time to market. Her vision for a future industry-scale chiplet ecosystem has been featured in Wired Magazine, AnandTech, and IEEE Spectrum. Previously, as Director of Strategic Technology Programs at Intel Labs, she led research in systems engineering and prototyping. Earlier, she delivered Intel’s first strained silicon technology, led the transition to 300 mm wafers, and did pathfinding for Hi-K metal gate and finfet transistors. She earned an MSEE in solid state physics from the University of California at Berkeley. 
 

Ali Keshavarzi, Ph.D.
Adjunct Professor
Electrical Engineering Department
Stanford University 

Ali Keshavarzi is involved in scholarly research and advises Stanford SystemX IoE Research. He also works with DARPA as an advisor and subject matter expert on the Electronic Resurgence Initiative (ERI). He is the founder of Leading Edge Research LLC, Los Altos, CA, and has been at the forefront of technology innovation, delivering process technologies, devices, circuits, SoCs, and modules to the semiconductor industry. He was Vice President of R&D and a Fellow at Cypress Semiconductor and previously held positions at Intel, TSMC, and GLOBALFOUNDRIES. He earned his Ph.D. in electrical and computer engineering from Purdue University, holds more than 60 U.S. patents, and has written more than 70 peer-reviewed papers.
 

Geoffrey Yeap, Ph.D.
Senior Director
Advanced Technology
Taiwan Semiconductor Manufacturing Company, Ltd.

Geoffrey Yeap works on TSMC’s flagship advanced technology platform. Previously, he was a Vice President of Engineering at Qualcomm Technologies Inc., leading silicon technology and foundry engineering and foundry IP/design enablement. He has more than 25 years of semiconductor industry experience at TSMC, Qualcomm, Motorola, and Advanced Micro Devices on high-performance microprocessor and mobile silicon technology development, introduction and manufacturing, and co-optimization. He earned a Ph.D. in electrical and computer engineering specializing in microelectronics from The University of Texas at Austin.  An IEEE Senior Member, he has published more than 55 refereed journal/conference papers.  
 

Moderator

Regina Freed
Managing Director
Patterning Technology Development
Applied Materials, Inc.

Regina Freed has more than 20 years of experience in the semiconductor industry, managing materials engineering, lithography, metrology, and defect inspection development for both logic and memory processes. Before joining Applied, she worked at KLA-Tencor and several semiconductor start-up companies, focusing on R&D, strategic marketing, and product development. She holds a M.S. in applied physics from the University of Twente in the Netherlands.